The present invention relates generally to integrated circuits, and, more particularly, to a voltage switching system for an integrated circuit.
Integrated circuits (IC) include various analog and digital circuits such as operational amplifiers, voltage regulators, power management controllers (PMC), sensors, logic circuits, and non-volatile memories. These circuits may be active or inactive at various times depending on operational requirements. An IC may be configured to operate in various operational modes such as run, standby, wait, etc., with the various modes activating and inactivating these circuits.
To reduce power consumption, the IC may operate at different voltage levels and have circuit domains that operate at different voltage levels. To facilitate operation at different voltage levels, multiple voltage regulators are required. For example, the IC may include a high power voltage regulator that provides a high supply voltage signal at a high voltage level (VHPVDD) and a low power voltage regulator that provides a low supply voltage signal at a low voltage level (VULPVDD). Then, in operation, the IC operates at the high voltage level in run mode and at the low voltage level in standby mode. The high voltage level VHPVDD could be, for example, 1.2V, and the low voltage level VULPVDD 1.125V.
Circuits that are active in a particular operational mode are sometimes referred to as a domain, such as a high power domain and a low power domain. The high power domain may be active in the run mode and inactive in the standby mode, while the low power domain may be active in both the run and standby modes.
FIG. 1 is a schematic block diagram of a conventional voltage switching system 102 connected to an IC 104. The IC 104 is operable in multiple operational modes such as run and standby modes. The voltage switching system 102 includes a high power voltage regulator (HPREG) 106a, an ultra-low power voltage regulator (ULPREG) 106b, and a PMOS transistor 108. The IC 104 includes high and low power domains 110a and 110b. The HPREG 106a and the high power domain 110a are operable in the run mode and are switched off in the standby mode, and the ULPREG 106b and the low power domain 110b are operable when the IC 104 is in run and standby modes.
The HPREG 106a has a first input terminal connected to a reference voltage generator (not shown) for receiving a first reference voltage signal, a second input terminal for receiving a first regulated voltage signal, and an output terminal connected to its second input terminal for generating the first regulated voltage signal. The ULPREG 106b has a first input terminal connected to the reference voltage generator for receiving a second reference voltage signal, a second input terminal for receiving a second regulated voltage signal, and an output terminal connected to its second input terminal for generating the second regulated voltage signal. The first and second reference voltage signals are at a high voltage level VHPVDD and a low voltage level VULPVDD, respectively. The HPREG 106a generates the first regulated voltage signal at the high voltage level VHPVDD, and the ULPREG 106b generates the second regulated voltage signal at the low voltage level VULPVDD.
The PMOS transistor 108 has a source terminal connected to the output terminal of the HPREG 106a for receiving the first regulated voltage signal, a gate terminal connected to a controller (not shown) for receiving a control signal, and a drain terminal connected to the output terminal of the ULPREG 106b for receiving the second regulated voltage signal. The controller is a PMC that generates the control signal when the IC transitions between the run and standby modes. The controller generates the control signal as a step voltage signal. The high and low power domains 110a and 110b are connected to the HPREG 106a and the ULPREG 106b for receiving the first and second regulated voltage signals, respectively.
When the IC 104 is in the run mode, the HPREG 106a provides the first regulated voltage signal to the high power domain 110a. The ULPREG 106b is switched off. The control signal generated by the controller is at a logic low state. The gate terminal of the transistor 108 receives the low control signal and the transistor 108 is switched on. As the transistor 108 is switched on, the HPREG 106a provides the first regulated voltage signal to the low power domain 110b. Thus, the HPREG 106a provides a first load current to the high and low power domains 110a and 110b. 
When the IC 104 is in standby mode, the HPREG 106a is switched off, the ULPREG 106b provides the second regulated voltage signal to the low power domain 110b, and the control signal generated by the controller is at a logic high state. The gate terminal of the transistor 108 receives the high control signal and the transistor 108 is switched off. Thus, the high power domain 110a does not receive either of the first or the second regulated voltage signals and hence, is inactive. The ULPREG 106b provides a second load current to the low power domain 110b. 
When the IC 104 transitions from the run mode to the standby mode, the HPREG 106a is switched off and the ULPREG 106b is switched on. It is well known in the art that the ULPREG 106b has a finite response time. The response time of the ULPREG 106b is defined as the time required by the ULPREG 106b for generating the second regulated voltage signal based on the second reference voltage signal. However, during the transition from the run mode to the standby mode, the HPREG 106a may be switched off before the ULPREG 106b generates the second regulated voltage signal. Thus, the ULPREG 106b is unable to generate the second load current required to power the low power domain 110b before the HPREG 106a is switched off. As a result, the low power domain 110b receives the second regulated voltage signal at a voltage level that is not within an operating voltage range of the IC 104, thereby causing the IC 104 to reset. Hence, there is a need to ensure that the transition between the operational modes of the IC does not result in a reset condition.
One known technique to overcome the aforementioned problem uses a capacitor (not shown) connected to the output terminal of the ULPREG 106b. When the IC 104 is in the run mode, the capacitor receives the first regulated voltage signal and stores a charge corresponding to the high voltage level VHPVDD of the first regulated voltage signal. When the IC 104 transitions from the run to standby mode, the capacitor discharges and provides the first regulated voltage signal at the high voltage level VHPVDD to the low power domain 110b for a short time period. This short time period corresponds to the discharge time period of the capacitor. During the discharge time period, the ULPREG 106b generates the second regulated voltage signal at the low voltage level VULPVDD and provides the second regulated voltage signal to the low power domain 110b. However, the discharge time period may not be equal to the response time of the ULPREG 106b. Thus, there is a possibility of the IC 104 being reset due to a mismatch between the discharge time of the capacitor and response time of the ULPREG 106b. When the discharge time period is less than the response time of the ULPREG 106b, the ULPREG 106b is unable to generate the second load current to power the low power domain 110b before the capacitor discharges, thereby causing the IC 104 to reset.
Therefore it would be advantageous to have a voltage switching system that prevents a reset of the IC when the IC transitions between different operational modes.